1. Field of the Invention
The present invention relates to a display, or in particular to a display having shift register circuits.
2. Description of the Background Art
A conventional inverter circuit of resistance load type having a load resistance is known. This inverter circuit is disclosed, for example, in Seigo Kishino: “Basis of Semiconductor Device” published by Ohmsha, Ltd., pp. 184-187, Apr. 25, 1985.
Also, a conventional shift register circuit having the inverter circuit of resistance load type described above is known. The shift register circuit is used with a circuit for driving the gate line and the drain line of, for example, a liquid crystal display and an organic EL display. FIG. 13 is a circuit diagram of the conventional shift register circuit having an inverter circuit of resistance load type. The conventional first-stage shift register circuit 104a1 shown in FIG. 13 is configured of a first circuit section 104b1 and a second circuit section 104c1. The shift register circuit 104a2 in the stage following the shift register circuit 104a1 is configured of a first circuit section 104b2 and a second circuit section 104c2.
The first circuit section 104b1 of the first-stage shift register circuit 104a includes n-channel transistors NT101, NT102, a capacitor C101 and a resistor R101. In the description of the prior art that follows, the n-channel transistors NT101, NT102, NT103 are referred to as the transistors NT101, NT102, NT103, respectively. The drain of the transistor NT101 is supplied with a start signal ST, and the source thereof is connected to a node ND101. The gate of the transistor NT101 is connected to a clock signal line CLK1. Also, the source of the transistor NT102 is connected to the negative potential (VSS), and the drain thereof is connected to a node ND102. Further, one of the electrodes of the capacitor C101 is connected to the negative potential (VSS), and the other electrode thereof is connected to the node ND101. A resistor R101 is interposed between the node ND102 and the positive potential (VDD). The transistor NT102 and the resistor R101 make up an inverter circuit.
The second circuit section 104c1 of the first-stage shift register circuit 104a1 is configured of an inverter circuit including a transistor NT103 and a resistor R102. The source of the transistor NT103 is connected to the negative potential (VSS), while the drain thereof is connected to the node ND103. The gate of the transistor NT103 is connected to the node ND102 of the first circuit section 104b1. A resistor R102 is interposed between the node ND103 and the positive potential (VDD). An output signal SR1 of the first-stage shift register circuit 104a1 is output from the node ND103. The node ND103 is connected with the first circuit section 104b2 of the second-stage shift register circuit 104a2.
The shift register circuits in the second and subsequent stages are configured similarly to the first-stage shift register circuit 104a1. The first circuit section of the shift registers in the following stage is connected to the output node of the shift register circuit in the preceding stage.
FIG. 14 is a timing chart of the conventional shift register circuit shown in FIG. 13. Next, with reference to FIGS. 13 and 14, the operation of the conventional shift register circuit is explained.
First, a L-level start signal ST is input as an initial mode. After the start signal ST is raised to H level, the clock signal CLK1 is raised to H level. As a result, the gate of the transistor NT101 of the first circuit section 104b1 of the first-stage shift register circuit 104a1 is supplied with the H-level clock signal CLK1, thereby turning on the transistor NT101. Thus, the H-level start signal ST is applied to the gate of the transistor NT102 thereby to turn on the transistor NT102. The potential of the node ND102 is then reduced to L level, and therefore the transistor NT103 is turned off. The potential of the node ND103 increases so that a H-level signal is output as an output signal SR1 from the first-stage shift register 104a1. This H-level signal is supplied also to the first circuit section 104b2 of the second-stage shift register circuit 104a2. By the way, the H-level potential is stored in the capacitor C101 as long as the clock signal CLK1 is at H level.
Next, the clock signal CLK1 is reduced to L level. As a result, the transistor NT101 is turned off. After that, the start signal ST is reduced to L level. In the process, even though the transistor NT101 turns off, the potential of the node ND101 is held at H level by the H-level potential stored in the capacitor C101, and therefore the transistor NT102 is kept on. Since the potential of the node ND102 is held at L level, the gate potential of the transistor NT103 is held at L level. As a result, the transistor NT103 is kept off, and therefore, a H-level output signal continues to be output as an output signal SR1 from the second circuit section 104c1 of the first-stage shift register circuit 104a1.
The clock signal CLK2 input to the first circuit section 104b2 of the second-stage shift register circuit 104a2 is raised to H level. In the second-stage shift register circuit 104a2, therefore, the H-level clock signal CLK2 is input with the H-level output signal SR1 input from the first-stage shift register circuit 104a1. Thus, the operation similar to the first-stage shift register circuit 104a1 is performed. As a result, a H-level output signal SR2 is output from the second circuit section 104c2 of the second-stage shift register circuit 104a2.
After that, the clock signal CLK1 is raised again to H level. The transistor NT101 of the first circuit section 104b1 of the first-stage shift register circuit 104a1 is turned on. In the process, the potential of the node ND101 drops to L level since the start signal ST is at L level. The transistor NT102 turns off, and therefore the potential of the node ND102 is raised to H level. As a result, the transistor NT103 is turned on, and the potential of the node ND103 is reduced to L level from H level. The L-level output signal SR1 is output from the second circuit section 104c1 of the first-stage shift register circuit 104a1. By the operation described above, H-level output signals (SR1, SR2, SR3 and so forth) shifted in timing are sequentially output from the shift register circuits in the respective stages.
In the first-stage shift register circuit 104a1 of the conventional shift register circuit shown in FIG. 13, however, the transistor NT102 is held in on state during the period when the output signal SR1 is at H level, and therefore, a through current inconveniently flows between the positive potential VDD and the negative potential VSS through the resistor R101 and the transistor NT102. Also, during the L-level period of the output signal SR1, the transistor NT103 is held on, and therefore, the through current inconveniently flows between the positive potential (VDD) and the negative potential (VSS) through the resistor R102 and the transistor NT103. Regardless of whether the output signal SR1 is at H level or L level, therefore, the through current always inconveniently flows between the positive potential (VDD) and the negative potential (VSS). The shift register circuits in other stages also have a similar configuration to the first-stage shift register circuit 104a1. Like the first-stage shift register circuit 104a1, therefore, the through current always inconveniently flows between the positive potential VDD and the negative potential VSS regardless of whether the output signal is at H or L level. As a result, in the case where the conventional shift register circuit described above is used as a circuit for driving the gate line or the drain line of a liquid crystal display or an organic EL display, the problem is posed that the current consumption of the liquid crystal display or the organic EL display, as the case may be, increases.